A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to FIG. 1, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 which is fabricated within a semiconductor substrate 102. The scaled down MOSFET 100 having submicron or nanometer dimensions includes a drain extension junction 104 and a source extension junction 106 formed within an active device area 126 of the semiconductor substrate 102. The drain extension junction 104 and the source extension junction 106 are shallow junctions to minimize short-channel effects in the MOSFET 100 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET 100 further includes a drain contact junction 108 with a drain silicide 110 for providing contact to the drain of the MOSFET 100 and includes a source contact junction 112 with a source silicide 114 for providing contact to the source of the MOSFET 100. The drain contact junction 108 and the source contact junction 112 are fabricated as deeper junctions such that a relatively large size of the drain silicide 110 and the source silicide 114 respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET 100.
The MOSFET 100 further includes a gate dielectric 116 and a gate structure 118 which may be comprised of polysilicon. A gate silicide 120 is formed on the polysilicon gate structure 118 for providing contact to the gate of the MOSFET 100. The MOSFET 100 is electrically isolated from other integrated circuit devices within the semiconductor substrate 102 by shallow trench isolation structures 121. The shallow trench isolation structures 121 define the active device area 126, within the semiconductor substrate 102, where a MOSFET is fabricated therein.
The MOSFET 100 also includes a spacer 122 disposed on the sidewalls of the gate structure 118 and the gate dielectric 116. When the spacer 122 is comprised of silicon nitride (Si.sub.3 N.sub.4), then a spacer liner oxide 124 is deposited as a buffer layer between the spacer 122 and the sidewalls of the gate structure 118 and the gate dielectric 116.
As the dimensions of the MOSFET 100 are scaled down further, such as 50 nm (nanometers) for the gate length of the MOSFET 100 for example, the depth of the drain extension junction 104 and the source extension junction 106 is also scaled down to about 15-30 nm (nanometers). The depth of the drain extension junction 104 and the source extension junction 106 is desired to be small to minimize short-channel effects in the MOSFET 100 as the gate length of the MOSFET 100 is scaled down, as known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to FIG. 2, in the prior art, an extension junction dopant is implanted into exposed regions of the active device area 126 to form the drain extension junction 104 and the source extension junction 106 after formation of the gate structure 118 on the gate dielectric 116. A first thermal anneal process is then performed to activate the extension junction dopant within the drain extension junction 104 and the source extension junction 106. Thermal anneal processes for activating dopants are known to one of ordinary skill in the art of integrated circuit fabrication.
The temperature used during the first thermal anneal process is relatively low in a range of from about 500.degree. Celsius to about 900.degree. Celsius to minimize transient enhanced diffusion of the extension junction dopant within the drain extension junction 104 and the source extension junction 106. When the semiconductor substrate 102 is heated up, transient enhanced diffusion of the extension junction dopant may deepen the drain extension junction 104 and the source extension junction 106 undesirably resulting in increased short-channel effects, as known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to FIG. 3, in the prior art, after formation of the drain extension junction 104 and the source extension junction 106, spacers 122 are formed with the spacer liner 124 at the sidewalls of the gate structure 118. A contact junction dopant is implanted into the exposed regions of the active device area 126 of the semiconductor substrate to form the drain contact junction 108 adjacent the drain extension junction 104 and to form the source contact junction 112 adjacent the source extension junction 106. A second thermal anneal process is then performed to activate the contact junction dopant within the drain contact junction 108 and the source contact junction 112. Thermal anneal processes for activating dopants are known to one of ordinary skill in the art of integrated circuit fabrication.
Deep junctions are desired for the drain contact junction 108 and the source contact junction 112 such that a relatively large size of the drain silicide 110 and the source silicide 114 respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET 100. Thus, a relatively higher temperature above about 1000.degree. Celsius is used during the second thermal anneal for activating the contact junction dopant within the drain contact junction 108 and the source contact junction 112.
However, the drain extension junction 104 and the source extension junction 106 have already been formed before the second thermal anneal. When the semiconductor substrate 102 is heated up to the relatively high temperature used during the second thermal anneal, transient enhanced diffusion of the extension junction dopant may deepen the drain extension junction 104 and the source extension junction 106 undesirably resulting in increased short-channel effects.
Thus, a mechanism is desired for annealing the contact junction dopant within the drain and source contact junctions 108 and 112 at a relatively high temperature for formation of deep contact junctions 108 and 112 while forming the drain and source extension junctions 104 and 106 with shallow depth for minimizing short channel effects in the MOSFET.